Chemical mechanical polishing (CMP) is a field of semiconductor processing technology where mechanical processing operation by means of an abrasive agent interposed between a wafer and a polishing pad under pressure and chemical etching operation by the chemical action of slurry are carried out at the same time, and constitutes an essential process of global planarization technology in the manufacture of semiconductor chips of sub-micrometer scale.
FIG. 1 through FIG. 3 are sectional views of process explanatory of a method for planarizing the surface of a common semiconductor device by chemical mechanical polishing, exemplifying STI (shallow trench isolation) process.
With reference made to FIG. 1, after forming a pad oxide layer (12) made of silicon oxide (SiO2) and a nitride layer (14) made of silicon nitride (Si3N4) on a substrate (10) made of single crystal of silicon, a photoresist pattern (not shown) that delimits a trench region (16) for electrically isolating active regions of device is formed, and the nitride layer (14) is etched by using the photoresist as an etching mask, which is used as an etching mask to form the trench region (16) by etching the pad oxide layer (12) and the substrate (10) to a predetermined depth. Then the trench region (16) is filled and an oxide layer (18a) made of silicon oxide is formed by vapor deposition so as to have a certain height above the surface of the nitride layer (14).
Now referring to FIG. 2, a primary chemical mechanical polishing process is carried out on the oxide layer (18a) by using a silica slurry composition. The reason why a silica-based slurry is used is that a polishing agent based on silica slurry is constituted from particles generally smaller than those of a polishing agent based on ceria slurry, and has higher efficiency of polishing the oxide layer (18a) that includes surface irregularities.
Now referring to FIG. 3, a secondary chemical mechanical polishing process is carried out on the oxide layer (18b) that remains on the nitride layer (14) in FIG. 2, until the surface of the nitride layer (14) is exposed, thereby to achieve global planarization so that oxide layer (18c) fills only the trench region (16).
Meanwhile the surface of the substrate (10) is not smooth over the entire surface of the wafer in the case of the CMP process, thus giving rise to such a problem that sufficient global planarization cannot be achieved in case the density of the trench regions (16) varies across the wafer.
FIG. 4a is a sectional view showing the surface of a semiconductor substrate prior to the CMP process for the explanation of nanotopography, FIG. 4b is a schematic diagram showing the thickness of an oxide layer formed on the semiconductor substrate prior to the CMP process, FIG. 5a is a sectional view showing the surface of the semiconductor substrate of FIG. 4a after the semiconductor substrate has been subjected to the CMP process, and FIG. 5b is a schematic diagram showing the thickness of the oxide layer formed on the semiconductor substrate after the CMP process.
Referring to FIG. 4a, the oxide layer (22) having a predetermined thickness is formed by vapor deposition on the substrate (20) made of single crystal of silicon that constitutes a wafer. FIG. 4a depicts, in significantly exaggerated manner, the so-called nanotopography of the surface of the substrate (20), namely such a profile that is characterized by a wavy surface of certain wavelength and certain deviation in height. Nanotopography is generally defined by a wavelength (L) ranging from 0.2 to 20 mm and deviation in height (H) from 20 to 80 mm. The oxide layer (22) formed on the substrate (20) by vapor deposition also has a surface profile of wavy pattern having a certain wavelength, formed under the influence of the nanotopography of the surface of the substrate (20).
Even when the oxide layer (22) is formed with certain waviness on the surface under the influence of the nanotopography of the surface of the substrate (20) as shown in FIG. 4b, thickness of the oxide layer (22) formed by vapor deposition becomes constant over the entire surface of the substrate (20).
When the CMP process is applied to the substrate (20) shown in FIG. 4a as a global planarization process, although the surface becomes flat as shown in the sectional view of FIG. 5a, thickness of the oxide layer (22a) extracted from FIG. 5a shows significant deviation across the surface as shown in FIG. 5b. That is, since the substrate surface that makes contact with a polishing pad of the polishing apparatus is polished at a constant rate over the entire wafer, the oxide layer (22a) is under-polished and becomes thicker at a point located above a valley region of the substrate (20) surface as indicated by “A”, and is over-polished and becomes thinner at a point located above a peak region of the substrate (20) surface as indicated by “B”. “Y3” in the diagram indicates mean thickness of the oxide layer (22a) after polishing.
As a result, the CMP process carried out as the global planarization does not make the thickness of the oxide layer (22a) uniform, because of the nanotopography effect imposed by the surface of the substrate (20). Such a fact presents the following problems, when a constant thickness of a layer over the entire surface of the substrate (20) is required to be maintained. For example, in DRAM as a semiconductor memory device, in the case in which an oxide layer as a gate insulation film of an MOS transistor doesn't have a constant thickness across the entire wafer, the reliability of the device can be adversely affected by, for example, a malfunction of the semiconductor device due to a deviation in the voltage input to the MOS transistors.
In the case of a semiconductor substrate (10) where the trench region (16) shown in FIG. 3 is formed, too, if a portion where the trench region (16) is formed is located in the valley region of nanotopography, the portion is under-polished and the oxide layer (18c) remains on the nitride layer (14), too. In case the portion is located in the peak region, on the other hand, the portion is over-polished and the corresponding portion of the nitride layer (14) may be removed by polishing, thus resulting in very small margin for the CMP process.